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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad5334/ad5335/ad5336/ad5344 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ?analog devices, inc., 2000 2.5 v to 5.5 v, 500 a, parallel interface quad voltage-output 8-/10-/12-bit dacs ad5334 functional block diagram (other diagrams inside) v out a buffer gnd ad5334 v out b buffer v out c buffer v out d buffer power-on reset to all dacs and buffers power-down logic pd dac register 8-bit dac 8-bit dac input register v ref c/d inter- face logic v dd v ref a/b gain db 7 db 0 cs wr a0 a1 clr ldac . . . dac register input register dac register input register dac register input register 8-bit dac 8-bit dac 8-bit dac features ad5334: quad 8-bit dac in 24-lead tssop ad5335: quad 10-bit dac in 24-lead tssop ad5336: quad 10-bit dac in 28-lead tssop ad5344: quad 12-bit dac in 28-lead tssop low power operation: 500 a @ 3 v, 600 a @ 5 v power-down to 80 na @ 3 v, 200 na @ 5 v via pd pin 2.5 v to 5.5 v power supply double-buffered input logic guaranteed monotonic by design over all codes output range: 0? ref or 0? v ref power-on reset to zero volts simultaneous update of dac outputs via ldac pin asynchronous clr facility low power parallel data interface on-chip rail-to-rail output buffer ampli?rs temperature range: ?0 c to +105 c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control general description the ad5334/ad5335/ad5336/ad5344 are quad 8-, 10-, and 12-bit dacs. they operate from a 2.5 v to 5.5 v supply con- suming just 500 a at 3 v, and feature a power-down mode that further reduces the current to 80 na. these devices incorporate an on-chip output buffer that can drive the output to both sup- ply rails. the ad5334/ad5335/ad5336/ad5344 have a parallel inter face. cs selects the device and data is loaded into the input registers on the rising edge of wr . the gain pin on the ad5334 and ad5336 allows the output range to be set at 0 v to v ref or 0 v to 2 v ref . input data to the dacs is double-buffered, allowing simultaneous update of multiple dacs in a system using the ldac pin. on the ad5334, ad5335 and ad5336 an asynchronous clr input is also provided. this resets the contents of the input register and the dac register to all zeros. these devices also incorporate a power-on-reset circuit that ensures that the dac output powers on to 0 v and remains there until valid data is written to the device. the ad5334/ad5335/ad5336/ad5344 are available in thin shrink small outline packages (tssop). * protected by u.s. patent number 5,969,657; other patents pending.
rev. 0 C2C ad5334/ad5335/ad5336/ad5344?pecifications (v dd = 2.5 v to 5.5 v, v ref = 2 v. r l = 2 k to gnd; c l =200 pf to gnd; all speci?ations t min to t max unless otherwise noted.) b version 2 parameter 1 min typ max unit conditions/comments dc performance 3, 4 ad5334 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5335/ad5336 resolution 10 bits relative accuracy 0.5 4 lsb differential nonlinearity 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5344 resolution 12 bits relative accuracy 2 16 lsb differential nonlinearity 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 % of fsr gain error 0.1 1 % of fsr lower deadband 5 10 60 mv lower deadband exists only if offset error is negative upper deadband 10 60 mv v dd = 5 v. upper deadband exists only if v ref = v dd offset error drift 6 C12 ppm of fsr/ c gain error drift 6 C5 ppm of fsr/ c dc power supply rejection ratio 6 C60 db ? v dd = 10% dc crosstalk 6 200 vr l = 2 k ? to gnd, 2 k ? to v dd ; c l = 200 pf to gnd; gain = 0 dac reference input 6 v ref input range 0.25 v dd v v ref input impedance 180 k ? gain = 1. input impedance = r dac (ad5336/ad5344) 90 k ? gain = 2. input impedance = r dac (ad5336) 90 k ? gain = 1. input impedance = r dac (ad5334/ad5335) 45 k ? gain = 2. input impedance = r dac (ad5334) reference feedthrough C90 db frequency = 10 khz channel-to-channel isolation C90 db frequency = 10 khz output characteristics 6 minimum output voltage 4, 7 0.001 v min rail-to-rail operation maximum output voltage 4, 7 v dd C 0.001 v max dc output impedance 0.5 ? short circuit current 50 ma v dd = 5 v 20 ma v dd = 3 v power-up time 2.5 s coming out of power-down mode. v dd = 5 v 5 s coming out of power-down mode. v dd = 3 v logic inputs 6 input current 1 a v il , input low voltage 0.8 v v dd = 5 v 10% 0.6 v v dd = 3 v 10% 0.5 v v dd = 2.5 v v ih , input high voltage 2.4 v v dd = 5 v 10% 2.1 v v dd = 3 v 10% 2.0 v v dd = 2.5 v pin capacitance 3.5 pf power requirements v dd 2.5 5.5 v i dd (normal mode) all dacs active and excluding load currents. v dd = 4.5 v to 5.5 v 600 900 av ih = v dd , v il = gnd. v dd = 2.5 v to 3.6 v 500 700 ai dd increases by 50 a at v ref > v dd C 100 mv. i dd (power-down mode) v dd = 4.5 v to 5.5 v 0.2 1 a v dd = 2.5 v to 3.6 v 0.08 1 a notes 1 see terminology section. 2 temperature range: b version: C40 c to +105 c; typical speci?cations are at 25 c. 3 linearity is tested using a reduced code range: ad5334 (code 8 to 255); ad5335/ad5336 (code 28 to 1023); ad5344 (code 115 to 40 95). 4 dc speci?cations tested with outputs unloaded. 5 this corresponds to x codes. x = deadband voltage/lsb size. 6 guaranteed by design and characterization, not production tested. 7 in order for the ampli?er output to reach its minimum voltage, offset error must be negative. in order for the ampli?er output to reach its maximum voltage, v ref = v dd and offset plus gain error must be positive. speci?cations subject to change without notice.
rev. 0 C3C ad5334/ad5335/ad5336/ad5344 ac characteristics 1 b version 3 parameter 2 min typ max unit conditions/comments output voltage settling time v ref = 2 v. see figure 20 ad5334 6 8 s 1/4 scale to 3/4 scale change (40 h to c0 h) ad5335 7 9 s 1/4 scale to 3/4 scale change (100 h to 300 h) ad5336 7 9 s 1/4 scale to 3/4 scale change (100 h to 300 h) ad5344 8 10 s 1/4 scale to 3/4 scale change (400 h to c00 h) slew rate 0.7 v/ s major code transition glitch energy 8 nv-s 1 lsb change around major carry digital feedthrough 0.5 nv-s digital crosstalk 3 nv-s analog crosstalk 0.5 nv-s dac-to-dac crosstalk 3.5 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p. unbuffered mode total harmonic distortion C70 db v ref = 2.5 v 0.1 v p-p. frequency = 10 khz notes 1 guaranteed by design and characterization, not production tested. 2 see terminology section. 3 temperature range: b version: C40 c to +105 c; typical speci?cations are at 25 c. speci?cations subject to change without notice. timing characteristics 1, 2, 3 parameter limit at t min , t max unit condition/comments t 1 0 ns min cs to wr setup time t 2 0 ns min cs to wr hold time t 3 20 ns min wr pulsewidth t 4 5 ns min data, gain, hben setup time t 5 4.5 ns min data, gain, hben hold time t 6 5 ns min synchronous mode. wr falling to ldac falling. t 7 5 ns min synchronous mode. ldac falling to wr rising. t 8 4.5 ns min synchronous mode. wr rising to ldac rising. t 9 5 ns min asynchronous mode. ldac rising to wr rising. t 10 4.5 ns min asynchronous mode. wr rising to ldac falling. t 11 20 ns min ldac pulsewidth t 12 20 ns min clr pulsewidth t 13 50 ns min time between wr cycles t 14 20 ns min a0, a1 setup time t 15 0 ns min a0, a1 hold time notes 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figure 1. speci?cations subject to change without notice. (v dd = 2.5 v to 5.5 v. r l = 2 k to gnd; c l = 200 pf to gnd. all speci?ations t min to t max unless other- wise noted.) t 15 t 14 t 8 cs wr data, gain, hben ldac 1 ldac 2 clr notes: 1 synchronous ldac update mode 2 asynchronous ldac update mode a0, a1 t 1 t 2 t 5 t 3 t 13 t 4 t 7 t 6 t 9 t 10 t 11 t 12 figure 1. parallel interface timing diagram (v dd = 2.5 v to 5.5 v, all speci?ations t min to t max unless otherwise noted.)
rev. 0 ad5334/ad5335/ad5336/ad5344 C 4 C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5334/ad5335/ad5336/ad5344 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * (t a = 25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v digital input voltage to gnd . . . . . . . . C0.3 v to v dd + 0.3 v digital output voltage to gnd . . . . . . C0.3 v to v dd + 0.3 v reference input voltage to gnd . . . . C0.3 v to v dd + 0.3 v v out to gnd . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . C40 c to +105 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c tssop package power dissipation . . . . . . . . . . . . . . . (t j max C t a )/ ja mw ja thermal impedance (24-lead tssop) . . . . . 128 c/w ja thermal impedance (28-lead tssop) . . . . . 97.9 c/w jc thermal impedance (24-lead tssop) . . . . . . 42 c/w jc thermal impedance (28-lead tssop) . . . . . . 14 c/w reflow soldering peak temperature . . . . . . . . . . . . . . . . . . . . . . 220 +5/C0 c time at peak temperature . . . . . . . . . . . . .10 sec to 40 sec * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide model temperature range package description package option ad5334bru C40 c to +105 c tssop (thin shrink small outline package) ru-24 ad5335bru C40 c to +105 c tssop (thin shrink small outline package) ru-24 ad5336bru C40 c to +105 c tssop (thin shrink small outline package) ru-28 ad5344bru C40 c to +105 c tssop (thin shrink small outline package) ru-28
rev. 0 ad5334/ad5335/ad5336/ad5344 C 5 C ad5334 functional block diagram v out a buffer gnd ad5334 v out b buffer v out c buffer v out d buffer power-on reset to all dacs and buffers power-down logic pd dac register 8-bit dac 8-bit dac input register v ref c/d inter- face logic v dd v ref a/b gain db 7 db 0 cs wr a0 a1 clr ldac . . . dac register input register dac register input register dac register input register 8-bit dac 8-bit dac 8-bit dac ad5334 pin function descriptions pin no. mnemonic function 1v ref c/d unbuffered reference input for dacs c and d. 2v ref a/b unbuffered reference input for dacs a and b. 3v out a output of dac a. buffered output with rail-to-rail operation. 4v out b output of dac b. buffered output with rail-to-rail operation. 5v out c output of dac c. buffered output with rail-to-rail operation. 6v out d output of dac d. buffered output with rail-to-rail operation. 7 gnd ground reference point for all circuitry on the part. 8 cs active low chip select input. this is used in conjunction with wr to write data to the parallel inter face. 9 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 10 a0 lsb address pin for selecting which dac is to be written to. 11 a1 msb address pin for selecting which dac is to be written to. 12 ldac active low control input that updates the dac registers with the contents of the input registers. this allows all dac outputs to be simultaneously updated. 13 pd power-down pin. this active low control pin puts all dacs into power-down mode. 14 v dd power supply pin. this part can operate from 2.5 v to 5.5 v and the supply sho uld be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 15C22 db 0 Cdb 7 eight parallel data inputs. db 7 is the msb of these eight bits. 23 gain gain control pin. this controls whether the output range from the dac is 0Cv ref or 0C2 v ref 24 clr asynchronous active low control input that clears all input registers and dac registers to zeros. ad5334 pin configuration top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad5334 ldac a1 a0 wr cs v ref c/d v ref a/b v out a v out b gnd v out d v out c pd v dd db 0 db 1 db 2 clr gain db 7 db 6 db 3 db 4 db 5 8-bit
rev. 0 ad5334/ad5335/ad5336/ad5344 C 6 C ad5335 functional block diagram . . . . . . v out a buffer gnd ad5335 v out b v out c v out d to all dacs and buffers power-down logic pd dac register v ref c/d inter- face logic v dd v ref a/b hben db 7 db 0 cs wr a0 a1 clr ldac reset power-on reset high byte register buffer buffer buffer dac register dac register dac register low byte register high byte register high byte register high byte register low byte register low byte register low byte register 10-bit dac 10-bit dac 10-bit dac 10-bit dac ad5335 pin function descriptions pin no. mnemonic function 1v ref c/d unbuffered reference input for dacs c and d. 2v ref a/b unbuffered reference input for dacs a and b. 3v out a output of dac a. buffered output with rail-to-rail operation. 4v out b output of dac b. buffered output with rail-to-rail operation. 5v out c output of dac c. buffered output with rail-to-rail operation. 6v out d output of dac d. buffered output with rail-to-rail operation. 7 gnd ground reference point for all circuitry on the part. 8 cs active low chip select input. this is used in conjunction with wr to write data to the par allel interface. 9 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 10 a0 lsb address pin for selecting which dac is to be written to. 11 a1 msb address pin for selecting which dac is to be written to. 12 ldac active low control input that updates the dac registers with the contents of the input registers. this allows all dac outputs to be simultaneously updated. 13 pd power-down pin. this active low control pin puts all dacs into power-down mode. 14 v dd power supply pin. this part can operate from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 15C22 db 0 Cdb 7 eight parallel data inputs. db 7 is the msb of these eight bits. 23 hben this pin is used when writing to the device to determine if data is written to the high byte register or the low byte register. 24 clr asynchronous active low control input that clears all input registers and dac registers to zeros. ad5335 pin configuration top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad5335 ldac a1 a0 wr cs v ref c/d v ref a/b v out a v out b gnd v out d v out c pd v dd db 0 db 1 db 2 clr hben db 7 db 6 db 3 db 4 db 5 10-bit
rev. 0 ad5334/ad5335/ad5336/ad5344 C 7 C ad5336 functional block diagram v out a buffer gnd ad5336 v out b buffer v out c buffer v out d buffer power-on reset to all dacs and buffers power-down logic pd dac register input register v ref c inter- face logic v dd v ref b gain db 9 db 0 cs wr a0 a1 clr ldac . . . v ref a v ref d reset input register input register input register dac register dac register dac register 10-bit dac 10-bit dac 10-bit dac 10-bit dac ad5336 pin function descriptions pin no. mnemonic function 1v ref d unbuffered reference input for dac d. 2v ref c unbuffered reference input for dac c. 3v ref b unbuffered reference input for dac b. 4v ref a unbuffered reference input for dac a. 5v out a output of dac a. buffered output with rail-to-rail operation. 6v out b output of dac b. buffered output with rail-to-rail operation. 7v out c output of dac c. buffered output with rail-to-rail operation. 8v out d output of dac d. buffered output with rail-to-rail operation. 9 gnd ground reference point for all circuitry on the part. 10 cs active low chip select input. this is used in conjunc tion with wr to write data to the parallel interface. 11 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 12 a0 lsb address pin for selecting which dac is to be written to. 13 a1 msb address pin for selecting which dac is to be written to. 14 ldac active low control input that updates the dac registers with the contents of the input r egisters. this allows all dac outputs to be simultaneously updated. 15 pd power-down pin. this active low control pin puts all dacs into power-down mode. 16 v dd power supply pin. this part can operate from 2.5 v to 5.5 v and the supply should be decoupled w ith a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 17C26 db 0 Cdb 9 10 parallel data inputs. db 9 is the msb of these 10 bits. 27 gain gain control pin. this controls whether the output range from the dac is 0Cv ref or 0C2 v ref . 28 clr asynchronous active low control input that clears all input registers and dac registers to zeros. ad5336 pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad5336 ldac a1 a0 wr cs gnd v out d v ref c v ref b v ref a v out c v out b v out a v ref d pd v dd db 0 db 1 db 2 db 3 db 4 clr gain db 9 db 8 db 5 db 6 db 7 10-bit
rev. 0 ad5334/ad5335/ad5336/ad5344 C 8 C ad5344 functional block diagram v out a buffer gnd ad5344 v out b buffer v out c buffer v out d buffer power-on reset to all dacs and buffers power-down logic pd dac register input register v ref c inter- face logic v dd v ref b cs wr a0 a1 ldac v ref a v ref d . . . . . . db 11 db 0 input register input register input register dac register dac register dac register 12-bit dac 12-bit dac 12-bit dac 12-bit dac ad5344 pin function descriptions pin no. mnemonic function 1v ref d unbuffered reference input for dac d. 2v ref c unbuffered reference input for dac c. 3v ref b unbuffered reference input for dac b. 4v ref a unbuffered reference input for dac a. 5v out a output of dac a. buffered output with rail-to-rail operation. 6v out b output of dac b. buffered output with rail-to-rail operation. 7v out c output of dac c. buffered output with rail-to-rail operation. 8v out d output of dac d. buffered output with rail-to-rail operation. 9 gnd ground reference point for all circuitry on the part. 10 cs active low chip select input. this is used in conjunction with wr to write data to the parallel interface. 11 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 12 a0 lsb address pin for selecting which dac is to be written to. 13 a1 msb address pin for selecting which dac is to be written to. 14 ldac active low control input that updates the dac registers with the contents of the input r egisters. this allows all dac outputs to be simultaneously updated. 15 pd power-down pin. this active low control pin puts all dacs into power-down mode. 16 v dd power supply pin. this part can operate from 2.5 v to 5.5 v and the supply should be decoupled w ith a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 17C28 db 0 Cdb 11 12 parallel data inputs. db 11 is the msb of these 12 bits. ad5344 pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad5344 ldac a1 a0 wr cs gnd v out d v ref c v ref b v ref a v out c v out b v out a v ref d pd v dd db 0 db 1 db 2 db 3 db 4 db 11 db 10 db 9 db 8 db 5 db 6 db 7 12-bit
rev. 0 ad5334/ad5335/ad5336/ad5344 C 9 C terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the actual endpoints of the dac transfer function. typical inl versus code plot can be seen in figures 5, 6, and 7. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a speci?ed differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed mono- tonic by design. typical dnl versus code plot can be seen in figures 8, 9, and 10. offset error this is a measure of the offset error of the dac and the output ampli?er. it is expressed as a percentage of the full-scale range. if the offset voltage is positive, the output voltage will still be positive at zero input code. this is shown in figure 3. because the dacs operate from a single supply, a negative offset cannot appear at the output of the buffer ampli?er. instead, there will be a code close to zero at which the ampli?er output saturates (ampli?er footroom). below this code there will be a deadband over which the output voltage will not change. this is illustrated in figure 4. gain error this is a measure of the span error of the dac (including any error in the gain of the buffer ampli?er). it is the deviation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. this is illus- trated in figure 2. output voltage dac code positive gain error negative gain error actual ideal figure 2. gain error output voltage dac code positive offset gain error and offset error actual ideal figure 3. positive offset error and gain error output voltage dac code negative offset gain error and offset error amplifier footroom (~1mv) negative offset deadband codes actual ideal figure 4. negative offset error and gain error
rev. 0 ad5334/ad5335/ad5336/ad5344 C 10 C offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. dc power-supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in dbs. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac at mid- scale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another dac. it is expressed in v. reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being up dated (i.e., ldac is high). it is expressed in dbs. channel-to-channel isolation this is a ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference inputs of the other dacs. it is measured by grounding one v ref pin and applying a 10 khz, 4 v peak-to-peak sine wave to the other v ref pins. it is expressed in dbs. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the dac changes state. it is normally speci?ed as the area of the glitch in nv secs and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device but is measured when the dac is not being written to ( cs held high). it is speci?ed in nv-secs and is measured with a full-scale change on the digital input pins, i.e. from all 0s to all 1s and vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is expressed in nv secs. analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping ldac high. then pulse ldac low and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv secs. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with the ldac pin set low and monitoring the output of another dac. the energy of the glitch is expressed in nv secs. multiplying bandwidth the ampli?ers within the dac have a ?nite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac and the thd is a measure of the harmonics present on the dac output. it is measured in dbs.
rev. 0 ad5334/ad5335/ad5336/ad5344 C 11 C typical performance characteristics code inl error ?lsbs 1.0 0.5 ?.0 0 50 250 100 150 200 0 ?.5 t a = 25 c v dd = 5v figure 5. ad5334 typical inl plot code dnl error lsbs 050 250 100 150 200 0.1 0.2 0.3 0.3 0.1 0.2 0 t a = 25 c v dd = 5v figure 8. ad5334 typical dnl plot v ref v error lsbs 0.5 0.25 0.5 01 5 234 0 0.25 v dd = 5v t a = 25 c max inl max dnl min dnl min inl figure 11. ad5334 inl and dnl error vs. v ref code inl error lsbs 3 0 200 1000 400 600 800 0 1 2 3 2 1 t a = 25 c v dd = 5v figure 6. ad5335 typical inl plot code dnl error lsbs 0.4 0.4 600 400 800 1000 0 0.6 0.6 0.2 0.2 t a = 25 c v dd = 5v 200 0 figure 9. ad5335 typical dnl plot temperature c error lsbs 0.5 0.2 0.5 40 0 40 0 0.2 v dd = 5v v ref = 2v max inl 80 120 0.4 0.3 0.1 0.1 0.3 0.4 max dnl min inl min dnl figure 12. ad5334 inl error and dnl error vs. temperature code inl error lsbs 12 0 4 8 8 4 0 4000 1000 2000 3000 12 t a = 25 c v dd = 5v figure 7. ad5336 typical inl plot code dnl error lsbs 0.5 2000 3000 4000 0 1 1 0.5 t a = 25 c v dd = 5v 1000 0 figure 10. ad5336 typical dnl plot gain error temperature c error % 1 0.5 1 40 0 40 0 0.5 v dd = 5v v ref = 2v offset error 80 120 figure 13. ad5334 offset error and gain error vs. temperature
rev. 0 ad5334/ad5335/ad5336/ad5344 C 12 C gain error v dd volts error % 0.2 0.6 01 3 0 0.4 t a = 25 c v ref = 2v 46 0.5 0.3 0.2 0.1 0.1 25 offset error figure 14. offset error and gain error vs. v dd 0 t a = 25 c i dd a v dd v 2.5 3.0 3.5 4.0 4.5 5.0 5.5 100 200 300 400 500 600 figure 17. supply current vs. supply voltage v out a 5s ch1 ch2 ldac t a = 25 c v dd = 5v v ref = 5v ch1 1v, ch2 5v, time base= 1 s/div figure 20. half-scale settling (1/4 to 3/4 scale code change) 5v source sink/source current ma v out volts 5 0 01 3 4 46 1 2 3 25 3v source 3v sink 5v sink figure 15. v out source and sink current capability 0 2.5 i dd a v dd v 3.0 3.5 4.0 4.5 5.0 5.5 0.1 0.2 0.3 0.4 0.5 t a = 25 c figure 18. power-down current vs. supply voltage v dd ch1 ch2 v out a t a = 25 c v dd = 5v v ref = 2v ch1 2v, ch2 200mv, time base = 200 s/div figure 21. power-on reset to 0 v 0 zero-scale full scale dac code i dd a v dd = 5.5v v dd = 3.6v 100 200 300 400 500 600 t a = 25 c v ref = 2v figure 16. supply current vs. dac code v logic v i dd a 200 0 0 1 2345 400 600 800 1000 1200 1400 1600 1800 v dd = 5v v dd = 3v figure 19. supply current vs. logic input voltage ch1 500mv, ch2 5v, time base = 1 s/div ch1 ch2 t a = 25 c v dd = 5v v ref = 2v v out a pd
rev. 0 ad5334/ad5335/ad5336/ad5344 C 13 C i dd a frequency 300 350 600 400 450 500 550 v dd = 5v v dd = 3v figure 23. i dd histogram with v dd = 3 v and v dd = 5 v full-scale error %fsr 0 0.2 0 1 23456 v dd = 5v t a = 25 c v ref v 0.1 0.1 0.2 0.3 0.4 figure 26. full-scale error vs. v ref 500ns/div v out volts 0.919 0.920 0.921 0.922 0.923 0.924 0.925 0.926 0.927 0.928 0.929 figure 24. ad5344 major-code tran- sition glitch energy 750ns/div 1mv/div figure 27. dac-dac crosstalk frequency khz 10 40 0.01 20 30 0 10 db 0.1 1 10 100 1k 10k 50 60 figure 25. multiplying bandwidth (small-signal frequency response) functional description the ad5334/ad5335/ad5336/ad5344 are quad resistor- string dacs fabricated on a cmos process with resolutions of 8, 10, 10, and 12 bits, respectively. they are written to using a parallel interface. they operate from single supplies of 2.5 v to 5.5 v and the output buffer ampli?ers offer rail-to-rail output swing. the gain of the buffer ampli?ers in the ad5334 and ad5336 can be set to 1 or 2 to give an output voltage range of 0 to v ref or 0 to 2 v ref . the ad5335 and ad5344 have out- put buffers with unity gain. the devices have a power-down feature that reduces current consumption to only 80 na @ 3 v. digital-to-analog section the architecture of one dac channel consists of a reference buffer and a resistor-string dac followed by an output buffer ampli?er. the voltage at the v ref pin provides the reference voltage for the dac. figure 28 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by: vv d gain out ref n = 2 where: d = decimal equivalent of the binary code which is loaded to the dac register: 0C255 for ad5334 (8 bits) 0C1023 for ad5335/ad5336 (10 bits) 0C4095 for ad5344 (12 bits) n = dac resolution gain = output ampli?er gain (1 or 2) v out gain dac register input register resistor string output buffer amplifier v ref figure 28. single dac channel architecture
rev. 0 ad5334/ad5335/ad5336/ad5344 C 14 C resistor string the resistor string section is shown in figure 29. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the output ampli?er. the voltage is tapped off by closing one of the switches connecting the string to the ampli?er. because it is a string of resistors, it is guaranteed m onotonic. to output amplifier r r r r r v ref figure 29. resistor string dac reference input the dacs operate with an external reference. the reference inputs are unbuffered and have an input range of 0.25 v to v dd . the impedance per dac is typically 180 k ? for 0Cv ref mode and 90 k ? for 0C2 v ref mode. the ad5336 and ad5344 have separate reference inputs for each dac, while the ad5334 and ad5335 have a reference inputs for each pair of dacs (a/b and c/d). output ampli?r the output buffer ampli?er is capable of generating output voltages to within 1 mv of either rail. its actual range depends on v ref , gain, the load on v out , and offset error. if a gain of 1 is selected (gain = 0), the output range is 0.001 v to v ref . if a gain of 2 is selected (gain = 1), the output range is 0.001 v to 2 v ref . however because of clamping the maximum output is limited to v dd C 0.001 v. the output ampli?er is capable of driving a load of 2 k ? to gnd or v dd , in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output ampli?er can be seen in figure 15. the slew rate is 0.7 v/ s with a half-scale settling time to 0.5 lsb (at 8 bits) of 6 s with the output unloaded. see figure 20. parallel interface the ad5334, ad5336, and ad5344 load their data as a single 8-, 10-, or 12-bit word, while the ad5335 loads data as a low byte of 8 bits and a high byte containing 2 bits. double-buffered interface the ad5334/ad5335/ad5336/ad5344 dacs all have double- buffered interfaces consisting of an input register and a dac register. dac data and gain inputs (w hen available) are written to the input register under control of the chip select ( cs ) and write ( wr ). access to the dac register is controlled by the ldac function. when ldac is high, the dac register is latched and the input register may change state without affecting the contents of the dac register. however, when ldac is brought low, the dac register becomes transparent and the contents of the input regis ter are transferred to it. the gain control signal is also double-buffered and is only updated when ldac is taken low. this is useful if the user requires simultaneous updating of all dacs and peripherals. the user may write to all input registers individually and then, by pulsing the ldac input low, all out- puts will update simultaneously. double-buffering is also useful where the dac data is loaded in two bytes, as in the ad5335, because it allows the whole data word to be assembled in parallel before updating the dac register. this prevents spurious outputs that could occur if the dac register were updated with only the high byte or the low byte. these parts contain an extra feature whereby the dac register is not updated unless its input register has been updated since the last time that ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the input registers. in the case of the ad5334/ ad5335/ad5336/ad5344, the part will only update the dac register if the input register has been changed since the last time the dac register was updated. this removes unnecessary crosstalk. clear input ( clr ) clr is an active low, asynchronous clear that resets the input and dac registers. note that the ad5344 has no clr function. chip select input ( cs ) cs is an active low input that selects the device. write input ( wr ) wr is an active low input that controls writing of data to the device. data is latched into the input register on the rising edge of wr . load dac input ( ldac ) ldac transfers data from the input register to the dac register (and hence updates the outputs). use of the ldac function enables double buffering of the dac and gain data. there are two ldac modes: synchronous mode : in this mode the dac register is updated after new data is read in on the rising edge of the wr input. ldac can be tied permanently low or pulsed as in figure 1. asynchronous mode : in this mode the outputs are not up dated at the same time that the input register is written to. when ldac goes low the dac register is updated with the contents of the input register. high-byte enable input (hben) high-byte enable is a control input on the ad5335 only that determines if data is written to the high-byte input register or the low-byte input register. the low data byte of the ad5335 consists of data bits 0 to 7 at data inputs db 0 to db 7 , while the high byte consists of data bits 8 and 9 at data inputs db 0 and db 1 . db 2 to db 7 are ignored during a high byte write. see figure 30.
rev. 0 ad5334/ad5335/ad5336/ad5344 C 15 C db8 db9 x x x x high byte low byte x = unused bit db0 db1 db2 db3 db4 db5 db6 db7 xx figure 30. data format for ad5335 power-on reset the ad5334/ad5335/ad5336/ad5344 are provided with a power-on reset function, so that they power up in a de?ned state. the power-on state is: ? normal operation ?0 C v ref output range ? output voltage set to 0 v both input and dac registers are ?lled with zeros and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up. power-down mode the ad5334/ad5335/ad5336/ad5344 have low power con- sumption, dissipating typically 1.5 mw with a 3 v supply and 3 mw with a 5 v supply. power consumption can be further re duced when the dacs are not in use by pu tting them into power-down mode, which is selected by taking pin pd low. when the pd pin is high, the dacs work normally with a typical power consumption of 600 a at 5 v (500 a at 3 v). in power- down mode, however, the supply current falls to 200 na at 5 v (80 na at 3 v) when the dacs are powered down. not only does the supply current drop, but the output stage is also internally switched from the output of the ampli?er, making it open-circuit. this has the advantage that the outputs are three-state while the part is in power-down mode, and provides a de?ned input cond ition for whatever is connected to the outputs of the dac ampli?e rs. the output stage is illustrated in figure 31. resistor string dac power-down circuitry amplifier v out figure 31. output stage during power-down the bias generator, the output ampli?er, the resistor string, and all other associated linear circuitry are all shut down when the power-down mode is activated. however, the contents of the registers are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. this is the time from a rising edge on the pd pin to when the output voltage deviates from its power-down volt- age. see figure 22. table i. ad5334/ad5336/ad5344 truth table clr ldac cs wr a1 a0 function 1 1 1 x x x no data transfer 1 1 x 1 x x no data transfer 0 x x x x x clear all registers 11 0 0 ? 1 0 0 load dac a input register, gain a (ad5334/ad5336) 11 0 0 ? 1 0 1 load dac b input register, gain b (ad5334/ad5336) 11 0 0 ? 1 1 0 load dac c input register, gain c (ad5334/ad5336) 11 0 0 ? 1 1 1 load dac d input register, gain d (ad5334/ad5336) 1 0 x x x x update dac registers x = dont care. table ii. ad5335 truth table clr ldac cs wr a1 a0 hben function 1 1 1 x x x x no data transfer 1 1 x 1 x x x no data transfer 0 x x x x x x clear all registers 11 00 ? 1 0 0 0 load dac a low byte input register 11 00 ? 1 0 0 1 load dac a high byte input register 11 00 ? 1 0 1 0 load dac b low byte input register 11 00 ? 1 0 1 1 load dac b high byte input register 11 00 ? 1 1 0 0 load dac c low byte input register 11 00 ? 1 1 0 1 load dac c high byte input register 11 00 ? 1 1 1 0 load dac d low byte input register 11 00 ? 1 1 1 1 load dac d high byte input register 1 0 x x x x x update dac registers x = dont care.
rev. 0 ad5334/ad5335/ad5336/ad5344 C 16 C suggested databus formats in many applications the gain input of the ad5334 and ad5336 may be hard-wired. however, if more flexibility is required, it can be included in a data bus. this enables the user to software program gain, giving the option of doubling the resolution in the lower half of the dac range. in a bused system gain may be treated as a data input since it is written to the device during a write operation and takes effect when ldac is taken low. this means that the output ampli?er gain of multiple dac devices can be controlled using a common gain line. the ad5336 databus must be at least 10 bits wide and is best suited to a 16-bit databus system. examples of data formats for putting gain on a 16-bit databus are s hown in figure 32. note that any unused bits above the actual dac data may be used for gain. db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 gain x x ad5336 x x x = unused bit x figure 32. ad5336 data format for byte load with gain data on 8-bit bus applications information typical application circuits the ad5334/ad5335/ad5336/ad5344 can be used with a wide range of reference voltages and offer full, one-quadrant multiplying capability over a reference range of 0.25 v to v dd . more typically, these devices may be used with a ?xed, preci- sion reference voltage. figure 33 shows a typical setup for the devices when using an external reference connected to the refer- ence inputs. suitable references for 5 v operation are the ad780 and ref192. for 2.5 v operation, a suitable external reference would be the ad589, a 1.23 v bandgap reference. ad5334/ad5335/ ad5336/ad5344 v out * 0.1 f v dd = 2.5v to 5.5v v dd gnd ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v v ref * gnd v out v in ext ref *only one channel of v ref and v out shown 10 f figure 33. ad5334/ad5335/ad5336/ad5344 using external reference driving v dd from the reference voltage if an output range of zero to v dd is required, the simplest solution is to connect the reference inputs to v dd . as this supply may not be very accurate, and may be noisy, the devices may be powered from the reference voltage, for e xample using a 5 v reference such as the adm663 or adm666, as shown in figure 34. ad5334/ad5335/ ad5336/ad5344 v out * v dd gnd v ref * gnd v out(2) v in adm663/adm666 vset shdn sense 6v to 16v *only one channel of v ref and v out shown 0.1 f 10 f 0.1 f figure 34. using an adm663/adm666 as power and reference to ad5334/ad5335/ad5336/ad5344 bipolar operation using the ad5334/ad5335/ad5336/ad5344 the ad5334/ad5335/ad5336/ad5344 have been designed for single supply operation, but bipolar operation is achievable using the circuit shown in figure 35. the circuit shown has been con?gured to achieve an output voltage range of C5 v < v o < +5 v. rail-to-rail operation at the ampli?er output is achievable using an ad820 or op295 as the output ampli?er. the output voltage for any input code can be calculated as follows: v o = [(1 + r 4/ r 3) ( r 2/( r 1 + r 2) (2 v ref d / 2 n )] C r 4 v ref / r 3 where: d is the decimal equivalent of the code loaded to the dac, n is dac resolution and v ref is the reference voltage input. with: v ref = 2.5 v r1 = r3 = 10 k ? r2 = r4 = 20 k ? and v dd = 5 v. v out = (10 d/2 n ) C 5 ad5334/ad5335/ ad5336/ad5344 gnd v dd = 5v ext ref v out * ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v gnd v in v out v ref * v dd r3 10k r1 10k r2 20k r4 20k 5v +5v 5v *only one channel of v ref and v out shown 0.1 f 0.1 f 10 f figure 35. bipolar operation using the ad5334/ad5335/ ad5336/ad5344
rev. 0 ad5334/ad5335/ad5336/ad5344 C 17 C decoding multiple ad5334/ad5335/ad5336/ad5344 the cs pin on these devices can be used in applications to decode a number of dacs. in this application, all dacs in the system receive the same data and wr pulses, but only the cs to one of the dacs will be active at any one time, so data will only be written to the dac whose cs is low. if multiple ad5343s are being used, a common hben line will also be required to determine if the data is written to the high-byte or low-byte register of the selected dac. the 74hc139 is used as a 2- to 4-line decoder to address any of the dacs in the system. to prevent timing errors from oc- curring, the enable input should be brought to its inactive state while the coded address inputs are changing state. figure 36 shows a diagram of a typical setup for decoding multiple devices in a system. once data has been written sequentially to all dacs in a system, all the dacs can be updated simultaneously using a common ldac line. a common clr line can also be used to reset all dac outputs to zero (except on the ad5344). enable coded address 1g 1a 1b v dd v cc 74hc139 dgnd 1y0 1y1 1y2 1y3 a0 a1 hben wr ldac clr data inputs data inputs data inputs a1 a0 hben* wr ldac clr cs data inputs data bus *ad5335 only a1 a0 hben* wr ldac clr cs a1 a0 hben* wr ldac clr cs a1 a0 hben* wr ldac clr cs ad5334/ad5335/ ad5336/ad5344 ad5334/ad5335/ ad5336/ad5344 ad5334/ad5335/ ad5336/ad5344 ad5334/ad5335/ ad5336/ad5344 figure 36. decoding multiple dac devices ad5334/ad5335/ad5336/ad5344 as a digitally programmable window detector a digitally programmable upper/lower limit detector using two of the dacs in the ad5334/ad5335/ad5336/ad5344 is shown in figure 37. any pair of dacs in the device may be used, but for simplicity the description will refer to dacs a and b. care must be taken to connect the correct reference inputs to the reference source. the ad5334 and ad5335 have only two reference inputs, v ref a/b for dacs a and b and v ref c/d for dacs c and d. if dacs a and b are used (for example) then only v ref a/b is needed. dacs c and d and v ref c/d may be used for some other purpose. the ad5336 and ad5344 have separate reference inputs for each dac. the upper and lower limits for the test are loaded to dacs a and b which, in turn, set the limits on the cmp04. if a signal at the v in input is not within the programmed window, an led will indicate the fail condition. 5v 0.1 f 10 f ad5336/ad5344 gnd v ref a v dd v out a v ref b v out b v in fail pass 1k 1k pass/ fail 1/6 74hc05 1/2 cmp04 v ref figure 37. programmable window detector programmable current source figure 38 shows the ad5334/ad5335/ad5336/ad5344 used as the control element of a programmable current source. in this example, the full-scale current is set to 1 ma. the output volt- age from the dac is applied across the current setting resistor of 4.7 k ? in series with the 470 ? adjustment potentiometer, which gives an adjustment of about 5%. suitable transistors to place in the feedback loop of the ampli?er include the bc107 and the 2n3904, which enable the current source to operate from a minimum v source of 6 v. the operating range is deter- mined by the operating characteristics of the transistor. suitable ampli?ers include the ad820 and the op295, both having rail- to-rail operation on their outputs. the current for any digital input code and resistor value can be calculated as follows: igv d r ma ref n = () 2 where: g is the gain of the buffer ampli?er (1 or 2) d is the digital input code n is the dac resolution (8, 10, or 12 bits) r is the sum of the resistor plus adjustment potentiometer in k ? ad5334/ad5335/ ad5336/ad5344 gnd v dd = 5v ext ref v out * ad780/ref192 with v dd = 5v gnd v in v out v ref * v dd 4.7k 5v *only one channel of v ref and v out shown 0.1 f 0.1 f 10 f 470 load v source ad820/ op295 figure 38. programmable current source
rev. 0 ad5334/ad5335/ad5336/ad5344 C 18 C coarse and fine adjustment using the ad5334/ad5335/ ad5336/ad5344 two of the dacs in the ad5334/ad5335/ad5336/ad5344 can be paired together to form a coarse and ?ne adjustment func tion, as shown in figure 39. as with the window comparator previ- ously described, the description will refer to dacs a, and b and the reference connections will depend on the actual device used. dac a is used to provide the coarse adjustment while dac b provides the ?ne adjustment. varying the ratio of r1 and r2 will change the relative effect of the coarse and ?ne adjustments. with the resistor values shown the output ampli?er has unity gain for the dac a output, so the output range is zero to (v ref C 1 lsb). for dac b the ampli?er has a gain of 7.6 10 C3 , giving dac b a range equal to 2 lsbs of dac a. the circuit is shown with a 2.5 v reference, but reference volt- ages up to v dd may be used. the op amps indicated will allow a rail-to-rail output swing. gnd v dd = 5v ext ref ad780/ref192 with v dd = 5v v in v out r2 51.2k v out 5v 0.1 f 0.1 f 10 f ad5336/ad5344 gnd v ref a v dd v out a r1 390 v ref b v out b r4 390 r3 51.2k figure 39. coarse and fine adjustment power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5334/ad5335/ad5336/ad5344 is mounted should be designed so that the analog and digital sections are separated, and con?ned to certain areas of the board. if the device is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as closely as pos- sible to the device. the ad5334/ad5335/ad5336/ad5344 should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low imped- ance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching sig- nals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
rev. 0 ad5334/ad5335/ad5336/ad5344 C 19 C table iii. overview of ad53xx parallel devices part no. resolution dnl v ref pins settling time additional pin functions package pins singles buf gain hben clr ad5330 8 0.25 1 6 s tssop 20 ad5331 10 0.5 1 7 s tssop 20 ad5340 12 1.0 1 8 s tssop 24 ad5341 12 1.0 1 8 s tssop 20 duals ad5332 8 0.25 2 6 s tssop 20 ad5333 10 0.5 2 7 s tssop 24 ad5342 12 1.0 2 8 s tssop 28 ad5343 12 1.0 1 8 s tssop 20 quads ad5334 8 0.25 2 6 s tssop 24 ad5335 10 0.5 2 7 s tssop 24 ad5336 10 0.5 4 7 s tssop 28 ad5344 12 1.0 4 8 s tssop 28 table iv. overview of ad53xx serial devices part no. resolution no. of dacs dnl interface settling time package pins singles ad5300 8 1 0.25 spi 4 s sot-23, microsoic 6, 8 ad5310 10 1 0.5 spi 6 s sot-23, microsoic 6, 8 ad5320 12 1 1.0 spi 8 s sot-23, microsoic 6, 8 ad5301 8 1 0.25 2-wire 6 s sot-23, microsoic 6, 8 ad5311 10 1 0.5 2-wire 7 s sot-23, microsoic 6, 8 ad5321 12 1 1.0 2-wire 8 s sot-23, microsoic 6, 8 duals ad5302 8 2 0.25 spi 6 s microsoic 8 ad5312 10 2 0.5 spi 7 s microsoic 8 ad5322 12 2 1.0 spi 8 s microsoic 8 ad5303 8 2 0.25 spi 6 s tssop 16 ad5313 10 2 0.5 spi 7 s tssop 16 ad5323 12 2 1.0 spi 8 s tssop 16 quads ad5304 8 4 0.25 spi 6 s microsoic 10 ad5314 10 4 0.5 spi 7 s microsoic 10 ad5324 12 4 1.0 spi 8 s microsoic 10 ad5305 8 4 0.25 2-wire 6 s microsoic 10 ad5315 10 4 0.5 2-wire 7 s microsoic 10 ad5325 12 4 1.0 2-wire 8 s microsoic 10 ad5306 8 4 0.25 2-wire 6 s tssop 16 ad5316 10 4 0.5 2-wire 7 s tssop 16 ad5326 12 4 1.0 2-wire 8 s tssop 16 ad5307 8 4 0.25 spi 6 s tssop 16 ad5317 10 4 0.5 spi 7 s tssop 16 AD5327 12 4 1.0 spi 8 s tssop 16 visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/ad53xx.html
rev. 0 C 20 C c3830 C 2.5 C 4/00 (rev. 0) printed in u.s.a. ad5334/ad5335/ad5336/ad5344 outline dimensions dimensions shown in inches and (mm). 24-lead thin shrink small outline package tssop (ru-24) 24 13 12 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.311 (7.90) 0.303 (7.70) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 28-lead thin shrink small outline package tssop (ru-28) 28 15 14 1 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0

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